TIMEPIX in 65nm, further exploring the sub-ps timing regime.

Mar 14, 2023, 3:25 PM
20m
Bldg 53 / Room 1320 - Panofsky Auditorium (SLAC)

Bldg 53 / Room 1320 - Panofsky Auditorium

SLAC

2575 Sand Hill Rd Menlo Park, CA USA
Oral Tracking Tracking

Speakers

Gary Varner (University of Hawai'i at Manoa) Gary Varner (University of Hawaii)

Description

We update our sub-picosecond timing studies[1,2], which used a straw-man pixel detector (TIMEMPIX) in which timing information was used to substitute for micron spatial resolution, significantly reducing channel count and data volume. That study considered the 130nm CMOS technology node and we update and contrast the performance and power parameters in the 65nm CMOS technology node.

  1. P. Orel, P. Niknejadi, G.S. Varner, “Exploratory study of a novel low occupancy vertex detector architecture based on high precision timing for high luminosity particle colliders,” Nucl. Instr. Meth. A857 (2017) 31-41.
  2. P. Orel, G.S. Varner, “Femtosecond Resolution Timing in Multi-GS/s Waveform Digitizing ASICs,” IEEE Trans. Nucl. Sci. 64 (2017) 1950 - 1962.

Primary authors

Gary Varner (University of Hawai'i at Manoa) Gary Varner (University of Hawaii)

Presentation materials