Conveners
RDC4: Session #1 - (Readout and ASICs) Circuits and Architectures for 4D Tracking and Calorimetry
- Angelo Dragone (SLAC)
- Mitch Newcomer (University of Pennsylvania)
RDC4: Session #2 - Big Data Management
- Julia Gonski (SLAC)
- Angelo Dragone (SLAC)
RDC4: Session #3 - Cryogenic and Deep Cryogenics
- Mitch Newcomer (University of Pennsylvania)
RDC4: Session #4 - Methodologies, Tools, IC blocks, SoCs and Workforce Development
- Angelo Dragone (SLAC)
- Mitch Newcomer (University of Pennsylvania)
The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to about 40-50ps per hit, to reach 30-35ps per track with two detector layers. The ETROC2 is the first full size (16x16) prototype design and is fully compatible with the final chip specifications in terms of functionality. The ETROC2 has been extensively tested recently. In this talk, the...
4D trackers with ~10ps timing will be transformative at future collider experiments. Timing is crucial for reducing the combinatorial challenge of track reconstruction at extremely high pileup densities, it offers completely new handles to detect and trigger on long-lived particles (LLP), expands the reach to search for new phenomena, and enables particle-ID capabilities at low transverse...
The Compact Muon Solenoid (CMS) Experiment’s High Granularity Calorimeter (HGCAL) upgrade replaces the CMS electromagnetic and hadronic endcap calorimeters in preparation for the high-rate and high-radiation environment of the High Luminosity LHC. To effectively use the over 6 million channels of this highly-segmented “imaging” calorimeter, CMS is pioneering very front-end data compression...
Advances in timing detector technology require new specialized readout electronics. Applications demand high rep rates, below 10 ps time of arrival resolution and, low power. A possible path to achieve O(10 ps) time resolution is an integrated chip using Silicon Germanium (SiGe) technology. Using DoE SBIR funding, Anadyne, Inc. in collaboration with UC Santa Cruz has developed a prototype SiGe...
Detectors at future colliders will rely on the ability to perform 4D tracking with O(10ps) resolution. As a stepping stone towards these future detectors we have developed a prototype ASIC, Pebbles, that contains the Big Rock analog front-end and embedded testing circuits. The Big Rock front-end aims to achieve 50ps timing resolution while maintaining all other requirements from the current...
We introduce an Application Specific Integrated Circuit (ASIC) readout integrated circuit (ROIC) prototype designed using the CMOS 28 nm bulk process. This chip serves as a smart pixel concept test chip for the Phase III high luminosity upgrade of the large Hadron collider.
Our design demonstrates a synchronous 40MSPS analog-to-digital converter (ADC) at the frontend, enabling data...
We present the design and performance of the Fermilab CFD ASIC (FCFD) developed for front-end readout of detectors with fast signals such as LGAD. The FCFD includes a specially designed discriminator that makes its response robust against amplitude variations of the signal. The application of the CFD directly in the readout ASIC promises to be more reliable and reduces the need for complicated...
Implementing machine learning (ML) models in hardware has received considerable interest over the last several years from the physics community. The Python packages, hls4ml and conifer, has enabled porting models trained using Python ML libraries to register transfer level (RTL) code. Most of the attention, thus far, has been focused on porting ML models to commercial FPGAs or synthesized...
With the push for future high-energy physics detectors to move more processing to the edge in an effort to reduce data volumes at the earliest possible stage, the ability to use programmable digital logic further up the digital signal processing chain becomes increasingly important. While embedded Field-Programmable Gate Arrays (eFPGAs) built into Application-Specific Integrated Circuits...
In a standard active pixel sensor, every pixel records brightness information which is sent out to the acquisition system through some sort of readout mechanism. Depending on the experiment requirements, a readout mechanism ranging from a completely serial readout to a completely parallel readout has been proposed by the research community. Like every other circuit design, each readout...
Next-generation silicon pixel detectors with fine granularity will allow for precise measurements of particle tracks in both space and time. This will result in unprecedented data rates which will exceed those anticipated at the HL-LHC. A reduction in the size of pixel data must be applied at the collision rate of 40MHz in order to fully exploit the pixel detector information of every...
Based on deep-sub-micron CMOS processes, modern silicon pixel detectors exhibit large arrays of fine-pitch pixels. They are designed to provide
unprecedented precise information on particle detection, encoded in pixel addresses, energy, and Time-of-Arrival, and provide a large bandwidth for reading out this information. Information on the initiating particle interaction is determined from...
Cryogenic Process Design Kits (PDKs) are an indispensable tool in the design of complex integrated circuits across a wide spectrum of applications, from noble element detectors to Quantum Information Science, Superconducting Nanowire Single Photon Detectors (SNSPDs), and precision atomic clocks. The development of PDK-compatible SPICE models is a complex endeavor requiring test structures,...
The HYDRA Microelectronics Codesign collaboration is developing scalable superconducting nanowire sensors (SNSPD) and cryogenic readout combining superconducting nanocryotrons and cryoCMOS ASICs operating at 4K.
We will present the status of the development of superconducting nanowire devices and circuit architectures, scalable high-density interconnect architecture for large-format SNSPD...
RF system-on-chip (RFSoC) devices have been widely used for instrumentation development at SLAC for various physics experiments hosted by SLAC and other collaborators worldwide. To leverage the integrated RF data converters and the large amount of programmable logic resources in RFSoC, a new RFSoC-based readout for superconducting detectors of microwave SQUID multiplexers (µmux) or microwave...
In this talk, we present the progress on development of CMOS-based front-end application-specific integrated circuits (ASICs) for charge and light readout undertaken at Brookhaven National Laboratory. This design evolves from the LArASIC chip manufactured in 0.18 µm, that has been selected for charge readout in the liquid argon time protection chamber (LArTPC) in the phase I of DUNE. LArASIC...
Readout of low-intensity microwave signals over a wide bandwidth has become increasingly important for fundamental science. The high frequency allows high information transfer, which is ideal for multiplexing detectors and reducing low-frequency noise.
One specific experiment in need of frequency multiplexing is Ricochet. Ricochet aims to measure coherent neutrino scattering to search for...
The next generation CMB-S4 survey aims to map the Cosmic Microwave Background (CMB) with unparalleled sensitivity in order to measure and constrain a vast range of fundamental physics including inflation, exotic light relics, and dark energy. To meet its sensitivity goals, the experiment requires fielding about 500,000 photon-noise limited superconducting transition edge sensors (TES) in...
Fermilab is organizing a 3D Heterogeneous Integration Multi-Project Wafer (3DHI-MPW) run to meet the current advanced packaging needs of scientific instrumentation as well as to further the state-of-the-art in advanced packaging for small-volume users.
Our goals are to:
1. Leverage high density face-to-face/face-to-back wafer bonding for current and future projects
2. Start the first of...
SLAC Instrumentation has developed a set of open-source tools that provide an extensible firmware library (SURF), coupled with a robust build system (RUCKUS), and a power hardware abstraction and readout layer (ROGUE) which, when combined, support rapid firmware/software development. This package is gaining traction in the community, with partner labs utilizing and improving the open-source...
Future detector systems will require miniaturized, low mass, low electromagnetic interference (EMI), magnetic field tolerant, and radiation tolerant power converters. One approach is to use on-chip or on-module DC-DC converters. These converters typically use inductors as an energy storage element, which can by physically large compared to the electronics they power, and require EMI and...
We present the architectural design, prototype fabrication and and first results for the High Pitch digitizer System-on-Chip (HPSoC). The HPSoC is a high channel density and scalable waveform digitization ASIC with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip is being fabricated in 65nm technology and targets the following features:...
CRYO ASIC plays a vital role as the charge readout component in the nEXO experiment. Its primary purpose is to process signals from sensors situated within the liquid xenon chamber, facilitating the study of phenomena such as neutrinoless double-beta (0νββ) decay and other rare events. Featuring a compact system-on-chip (SoC) architecture in a small 7mm x 9mm form factor, its...
PSEC4 [1] has been utilized for waveform sampling in the PhD theses of E. Angelico[2] and E. Oberla[3] ,the Fermilab Test Beam, and the Accelerator Neutrino Neutron Interaction Experiment. PSEC5 aims to improve on its predecessor by raising the number of channels from 6 to 16, the sampling rate from 10 GSa/s to 40 GSa/s, and most importantly, achieving a timing resolution of 1 picosecond.
A...
