7–10 Nov 2023
SLAC
America/Los_Angeles timezone

SiGe integrated chip readout for fast timing

7 Nov 2023, 14:30
15m
48/1-112C/D - Redwood C/D (SLAC)

48/1-112C/D - Redwood C/D

SLAC

60
Oral RDC4: Readout and ASICs RDC4

Speakers

Gabriel Saffier-Ewing (Anadyne Inc.) Zachary Galloway (Anadyne Inc.)

Description

Advances in timing detector technology require new specialized readout electronics. Applications demand high rep rates, below 10 ps time of arrival resolution and, low power. A possible path to achieve O(10 ps) time resolution is an integrated chip using Silicon Germanium (SiGe) technology. Using DoE SBIR funding, Anadyne, Inc. in collaboration with UC Santa Cruz has developed a prototype SiGe front end readout chip optimized for low power and timing resolution (0.6 mW/channel, 10 ps of timing resolution for 8 fC). In this contribution the ASIC performance simulation and the results from the first prototype run will be shown.

Primary authors

Prof. Bruce Schumm (Santa Cruz Institute for Particle Physics and the University of California, Santa Cruz (US)) Gabriel Saffier-Ewing (Anadyne Inc.) Jennifer Ott (UCSC) Simone Mazza Zachary Galloway (Anadyne Inc.)

Presentation materials