Speaker
Description
Next generation high energy physics experiments face challenges with high data rates and stringent hardware constraints, driving the need for resources-efficient on-detector readout processing solutions. This work explores the novel application of embedded field programmable gate arrays (eFPGA) technology in detector readout systems. Leveraging eFPGA's unique combination of FPGA's reconfigurability and ASIC's low power consumption, we successfully implemented a proof-of-concept boosted decision tree (BDT) classifier for pileup track rejection and validated designs on 28nm CMOS chip using the open-source FABulous framework. Our eFPGA implementation achieved perfect reproduction of the BDT algorithm, demonstrating its viability for HEP applications. In parallel, variational autoencoder models were developed for data compression and real-time sensor defect monitoring, showing promise for reducing off-detector data rates at ultra low latency. These efforts advance ML inference in detector subsystems, with our eFPGA implementation providing a promising pathway for integrating ML algorithms in future collider subsystems.
