Conveners
RDC1 + RDC4: Session #1
- Mitch Newcomer (University of Pennsylvania)
- Jonathan Asaadi (University of Texas Arlington)
- Carmen Carmona (Pennsylvania State University)
- Angelo Dragone (SLAC)
We introduce GAMPix (Grid-Activated Multi-scale Pixel readout), a novel charge readout system for TPCs, that is designed to enhance the accuracy of electron track reconstruction to the sub-millimeter level, while also ensuring high energy reconstruction accuracy with a low power consumption. The GAMPix system operates using coarse wire grids paired with pixel planes. The signal generated from...
The LArPix charge readout system is designed to provide native 3D readout of ionization charge signals in liquid argon time projection chambers (LArTPCs) in a way that is scalable to instrument large volumes. The system is compatible with large-scale commercial fabrication techniques, which enables low-cost quick-turn production. At the heart of the system is the low-power, cryo-compatible,...
LightPix is an Application Specific Integrated Circuit (ASIC) geared towards highly scalable cryogenic SiPM readout. LightPix is manufactured in 180-nm Bulk CMOS, and provides 64 individual channels each with amplification, a self-triggering TDC with O(ns) precision, and digital readout. Each ASIC dissipates <200 $\mu$W per channel, and is scalable to >1000 channels per signal cable, allowing...
nEXO is a next-generation liquid xenon experiment to search for the neutrino-less double beta decay of $^{136}$Xe, with a lifetime sensitivity goal of greater than 10$^{28}$ years. The experiment will use an array of charge tiles composed of crossed metal strips to record ionization electrons. An in-xenon cryogenic application-specific integrated circuit (ASIC) named CRYO ASIC has been...
The Q-Pix concept (arXiv: 1809.10213) is a continuously integrating low-power charge-sensitive amplifier (CSA) viewed by a Schmitt trigger. When the trigger threshold is met, the comparator initiates a 'reset' transition and returns the CSA circuitry to a stable baseline. This is the elementary Charge-Integrate / Reset (CIR) circuit. The instance of reset time is captured in a 32-bit clock...
