4D Tracking

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ZOOM:

Hi there, 

Ariel Schwartzman is inviting you to a scheduled Zoom meeting. 

Topic: 4D Tracking
Time: Oct 28, 2020 12:00 PM Pacific Time (US and Canada)

Join from PC, Mac, Linux, iOS or Android: https://stanford.zoom.us/j/96761780433?pwd=NU1lZ1ZISlBCTkJkZk9FV3VjSlA2QT09
    Password: 244328

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    Meeting ID: 967 6178 0433
    Password: 244328
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    Meeting ID: 967 6178 0433
    Password: 244328
    SIP: 96761780433@zoomcrc.com
    Password: 244328

 

 

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  • Electronics ASIC design in new technologies requires significant learning (new design rules, new simulations, different effects). Working on 28/22nm technology will require enough time to learn, and more prototyping/tests. New licenses will also increase costs. 
  • Plan for an integrated design of the ASIC and the FPGA readout board. This will avoid all the pitfalls from the HGTD ALTIROC experience in which the FPGA board had to overcome challenges from an independent ASIC design that could not be modified.  
  • The consensus from the meeting is to consider a R&D effort to design and build a 28nm or 22nm fast timing TDC. This effort will be the first on its kind in HEP, and will uniquely position SLAC to significantly contribute to a future 4D tracking collaboration (for ATLAS LS4 or future collider) and push the collider timing frontier.
    • The design will include pre-amplifier, TDC, and readout electronics, and target 30ps time resolution with 50um pitch LGAD sensors. 
  • The next step is to consider in greater detail the pro/cons of 28nm vs 22nm technology, and start planning a concrete R&D program before looking for funding opportunities.  
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