Speaker
Description
As superconducting quantum processors scale up, physical layout decisions increasingly affect both system robustness and architectural scalability. In this poster, we present a physical-design perspective that connects two layout-driven challenges in quantum chip design. First, we study the placement of phonon and quasiparticle traps to mitigate the impact of cosmic-ray-induced events and other high-energy disturbances that can generate correlated errors across a chip. By strategically introducing absorbing structures, we aim to reduce the propagation of phonons and quasiparticles and improve the resilience of superconducting devices. Second, we develop a frequency-aware optimization framework for qubit and coupler placement that accounts for frequency compatibility while also supporting region-based placement constraints. These regional constraints enable the deliberate formation of modular substructures, such as chiplet-like partitions, within a larger quantum chip layout. Together, these two directions motivate a broader co-design methodology for quantum hardware physical design, in which robustness to error mechanisms and scalability-oriented layout organization are addressed within a unified optimization framework. This work highlights how physical layout can serve as a common design layer linking device-level protection and system-level modularity in next-generation quantum processors.
