Name: 4D Tracking, Vertexing, and HL-LHC Reconstruction
Start: 2025-10-03T13:00:00-07:00
End: 2025-10-03T14:30:00-07:00
Location: No location set

- 13:00 → 13:10
  4D Tracking and 4D Vertexing in Run 4
  - Comprehensive approach to 4D tracking, vertexing, vertex t0, PU suppression, VBF jet tagging and LLP using HGTD
  - Vertex t0 reconstruction
  - 4D Vertexing using ACTS
- 13:10 → 13:20
  Phase-III 4D Tracking ITk inner pixel replacement
  - Layout studies
  - Clustering (accounting for angles)
  - Track seeing (using timing and angles)
  - 4D tracking in ACTS
  - 4D vertexing in ACTS
  - Data reduction schemes (on-chip processing)
- 13:20 → 13:30
  Fast timing at Higgs Factories
  - FCC-ee silicon and colorimeter timing layers
    
    Physics case: LLP, Flavor physics, ...
    
    ACTS implementation of timing layer
    
    Vertex t0 studies
    
    Calorimeter timing layers
    
    Combination/interplay between silicon and calorimeter timing layers
    
    Inner tracker timing layer for vertex t0, BIB
    
    Novel applications of calorimeter timing for 5D Particle Flow
  - 4D Tracking at muon collider
    
    Combination of timing and angles
    
    Gating vs. timing
    
    In-pixel pileup → waveform ML on-chip processing
- 13:30 → 13:40
  Vertex Selection
  - Systematic study of vertex selection efficiency mistakes
  - SumPtW
  - Anomaly detection
  - Selection of 2 vertices
  - Run 3: incorporate fJVT in discriminant
- 13:40 → 13:50
  
  Multi-vertex interpretation and GNN Pileup suppression
- 13:50 → 14:00
  
  b-tagging using pileup vertex information
- 14:00 → 14:10
  
  Vertexing using jets
- 14:10 → 14:20
  HL-LHC event reconstruction
  - New approaches to HL-LHC reconstruction to address high luminosity challenges:
    
    forward tracking+timing
    
    hard-qcd jets
    
    overlapping jets
    
    jet-vertex association
    
    timing (HGTD+LAr)
    
    multi-vertex interpretation
    
    local pileup suppression
    
    E/P Pflow algorithm
- 14:20 → 14:30
  4D Tracking Detector R&D
  - 2D Vernier TDC
  - 3D Integration
  - Radhard LGAD
  - on-chip data reduction schemes
  - Calorimeter timing layers
  - US 4D-Tracker Demonstrator Project